Byte order, or “endianness” or “endian architecture” as it is also frequently referred to, should be familiar to one of skill in the art. Generally speaking, computer data normally comprises a plurality of digital words that are each formed from a multitude of different bytes, each byte typically being stored in an address of a memory array. When it is desired or necessary to break a large word into smaller words, the order in which the bytes of the smaller words are stored in memory can be important to recognition of the data by various computing devices. In other words, not all computing devices are designed to read data in the same order, i.e., not all computing devices have the same endianness.
There are two well-known and industry accepted byte order storage (endianness) formats or architectures that apply equally well to data structures whose representation requires two or more bytes of data, such as two byte integer values. These formats are known as big endian and little endian. In a big endian format, the most significant byte of data is stored in the lowest memory address. In a little endian format, the least significant byte of data is stored in the lowest memory address.
In addition to the big and little endian storage formats, there are two other popular byte order combinations that are applicable to data structures whose representation requires four or more bytes of data, such as Single Precision Floating Point (REAL) values and Double Integers (DINT's). The first of these alternative byte orders may follow the protocol of either the big endian or little endian format with respect to what byte is stored in the lowest memory address, however, there is a swapping of the bytes in each of the two byte words (for a total of four bytes). This byte order will be referred to herein as the “byte swap” byte order. The second of the alternative byte orders may again follow the protocol of either the big endian or little endian format with respect to what byte is stored in the lowest memory address, however, there is a swapping of the two byte word units (again, for a total of four bytes). This byte order will be referred to herein as the “word swap” byte order.
Issues relating to byte order conflicts often, but not exclusively, arise in the context of a data exchange/data sharing between two computing devices (e.g., a computing system/control device and a peripheral device). As should be apparent, a computing device that is provided with data in one architecture while expecting the other, may read the data in the opposite direction from that intended or otherwise not understand the data that is received.
In light of the aforementioned potential endianness conflicts, devices and techniques have been developed to help ensure that data transfers between devices occur with a proper byte order. On a most basic level, a number of devices are designed and constructed to permit byte order configuration by a user. For example, knowing the endianness of the controlling device, a user may configure the endianness of a peripheral device from which data will be received. Such a configuration may occur manually or through software. A primary drawback to this technique is, of course, that the user is required to know the proper byte order and also understand how to set the byte order on the appropriate device.
Other proper byte ordering techniques and devices have also been developed. One such device is a bi-endian processor, which may selectively operate in either big endian or little endian mode based on the placement of a jumper or based on the output of a special selection circuit. Byte swapping techniques have also been developed to deal with endianness conflicts between computing systems and associated peripheral devices. According to one such technique, the endianness of the computing system is set in a configuration register, the endian information of the peripheral devices is read and compared to the stored endianness of the computing system, and if there is a conflict, the peripheral device data is byte-swapped before transfer to the computing device. Other similar byte-swapping techniques are also known, including those that employ a physical byte swapping device or specialized byte-swapping software between the data-transferring device and data-receiving device of interest. In each such case, however, it is believed that the endianness of the controlling system/device must be known or the controlling system/device must be used to determine the endianness of a peripheral device(s) of interest and to cause a byte swap to occur if an endianness mismatch is discovered.
While known devices and techniques for reconciling byte order conflicts are no doubt useful, it should also be apparent that these devices and techniques have various limitations and drawbacks. Perhaps paramount in this regard is the requirement of knowing the endianness of the computing/controlling system or using the computing/controlling system to cause a byte swap to occur subsequent to the transmission of data by a peripheral or other device in communication with the computing/controlling system. Exemplary inventive embodiments described herein are believed to overcome such limitations and drawbacks.